1. Field of the Invention
The invention relates to a semiconductor process, and more particularly related to a lateral diffused metal oxide semiconductor transistor (LDMOS).
2. Description of the Related Art
Power semiconductor devices are currently in wide use in many electronic products and the most common devices for high voltage integrated circuits are lateral diffused metal oxide semiconductor transistors (LDMOS). The LDMOS has advantages of specific on resistance and breakdown voltage and is capable of being integrated by a VLSI process.
Referring to FIG. 1, which shows a cross section of a conventional lateral diffused MOS transistor, a p-typed epitaxy layer 104 (also referred to as a p well) is disposed on a p-type silicon substrate 102, and an n well 106 is disposed in the p-type epitaxy layer 104. A plurality of field oxide layers (FOX) 108 are partially disposed on the p-typed epitaxy layer 104 and the n well 106. A gate structure 114 including a gate electrode 110 and a gate dielectric layer 112 is disposed on a portion of the p-type epitaxy 104, the n well 106 and the field oxide layer 108. An N+ source 116 formed by ion implantation is disposed on a side of the gate structure 114 and a N+ drain 118 is adjacent to the field oxide layer 108 neighboring the gate structure 114. Isolation between devices of the LDMOS can be increased by forming the field oxide 108 or extending well regions. The two methods, however, increase device size, which is contrary to miniaturization trends.